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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M37733S4BFP is a microcomputer using the 7700 Family core. This microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the RAM, multiple-function timers, serial I/O, A-D converter, and so on.
qProgrammable input/output (ports P4, P5, P6, P7, P8) ........................................................ 37 qClock generating circuit ........................................ 2 circuits built-in
APPLICATION
Control devices for general commercial equipment such as office automation, office equipment, personal information equipment, and so on. Control devices for general industrial equipment such as communication equipment, and so on.
FEATURES
qNumber of basic instructions .................................................. 103 qMemory size RAM ................................................ 2048 bytes qInstruction execution time The fastest instruction at 25 MHz frequency ...................... 160 ns qSingle power supply .................................................... 5 V 10 % qLow power dissipation (At 25 MHz frequency)....... 47.5 mW (Typ.) qInterrupts ............................................................ 19 types, 7 levels qMultiple-function 16-bit timer ................................................. 5 + 3 qSerial I/O (UART or clock synchronous)..................................... 3 q10-bit A-D converter .............................................. 8-channel inputs q12-bit watchdog timer
PIN CONFIGURATION (TOP VIEW)
P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P22/A18/D2 P23/A19/D3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TXD2 P74/AN4/RXD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9
40 39 38 37 36 35 34
M37733S4BFP
33 32 31 30 29 28 27 26 25
P24/A20/D4 P25/A21/D5 P26/A22/D6 P27/A23/D7 P30/R/W P31/BHE P32/ALE P33/HLDA VSS E XOUT XIN
RESET
CNVSS BYTE
HOLD
P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT/KI2/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT/KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47 P46 P45 P44 P43 P42/ 1
Outline 80P6N-A
RDY
2
Reset input
RESET
M37733S4BFP BLOCK DIAGRAM
Enable output VCC AVCC (0V) VSS CNVss (0V) AVSS Reference External data bus width voltage input selection input VREF BYTE
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Clock input Clock output XIN XOUT
E
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XCIN XCOUT Instruction Register(8)
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Clock Generating Circuit
Incrementer(24)
Stack Pointer S(16)
Index Register Y(16)
Index Register X(16)
Accumulator B(16)
Data Buffer DBL(8)
Data Bank Register DT(8)
Data Buffer DBH(8)
Input Butter Register IB(16)
Program Address Register PA(24)
Processor Status Register PS(11)
Program Counter PC(16)
Direct Page Register DPR(16)
Data Address Register DA(24)
Instruction Queue Buffer Q0(8)
Instruction Queue Buffer Q2(8)
Program Bank Register PG(8)
Instruction Queue Buffer Q1(8)
Incrementer/Decrementer(24)
Accumulator A(16)
Arithmetic Logic Unit(16)
Timer TA4(16) Watchdog Timer Timer TB2(16) UART2(9) UART1(9) UART0(9) A-D Converter(10) Timer TB1(16) Timer TB0(16)
Timer TA3(16)
RAM
Timer TA2(16)
Data Bus(Odd)
2048 bytes
Timer TA1(16)
Data Bus(Even)
Address Bus
Timer TA0(16)
XCOUT XCIN
P8(8)
P7(8)
P6(8)
P5(8)
P4(5)
Address higher middler/data (16)
Address lower (8)
1
RDY HOLD HLDA ALE BHE R/W
MITSUBISHI MICROCOMPUTERS
M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Input/Output port P8
Input/Output port P7
Input/Output port P6
Input/Output port P5
Input/Output port P4
Address bus/Data bus
Address bus
MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37733S4BFP
Parameter Number of basic instructions Instruction execution time Memory size Input/Output ports Multi-function timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Memory expansion Operating temperature range Device structure Package Input/Output voltage Output current Functions 103 160 ns (the fastest instruction at external clock 25 MHz frequency) 2048 bytes 8-bit ! 4 5-bit ! 1 16-bit ! 5 16-bit ! 3 (UART or clock synchronous serial I/O) ! 3 10-bit ! 1 (8 channels) 12-bit ! 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 - 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 5 V 10 % 47.5 mW (at external clock 25 MHz frequency) 5V 5 mA Maximum 16 Mbytes -20 to 85 C CMOS high-performance silicon gate process 80-pin plastic molded QFP (80P6N-A)
RAM P5 - P8 P4 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2
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Pin Vcc, Vss CNVss _____
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Name Input/Output Power source Apply 5 V 10 % to Vcc and 0 V to Vss. CNVss input Reset input Clock input Clock output Enable output Bus width selection input Input Input Input Output Output Input Functions
XIN
_
XOUT
E
BYTE
AVcc, AVss VREF
Analog power source input Reference voltage input P00/A0 - Address (lowP07/A7 order) output P10/A8/D8 - Address (middle P17/A15/D15 -order) output/data (high-order) I/O P20/A16/D0 - Address (highP27/A23/D7 order) output/data (low-order) I/O _ P30/R/W Read/Write output ___ P31/BHE Byte high enable output P32/ALE Address latch enable output ____ P33/HLDA Hold acknowHOLD
___
Connect to Vcc. When "L" level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz-crystal oscillator between XIN and XOUT. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. _ When output level of E signal is "L", data/instruction read or data write is performed. This pin determines whether the external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when "L" signal is input and an 8-bit width when "H" signal is input. Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. This is reference voltage input pin for the A-D converter. Address (A0 - A7) is output. When the BYTE pin is set to "L" and external data bus has a 16-bit width, high-order data (D8 - D15) is input/output or an address (A8 - A15) is output. When the BYTE pin is "H" and an external data bus has an 8-bit width, only address (A8 - A15) is output. Low-order data (D0 - D7) is input/output or an address (A16 - A23) is output.
Input Output I/O
I/O
Output Output Output Output Input Input Output I/O I/O I/O
"H" indicates the read status and "L" indicates the write status. "L" is output when an odd-numbered address is accessed. This is used to retrieve only the address from address and data multiplex signal. This outputs "L" level when the microcomputer enters hold state after a hold request is accepted.
____
____
RDY
ledge output Hold request input Ready input
P42/ 1 P43 - P47 P50 - P57 P60 - P67
Clock output I/O port P4 I/O port P5 I/O port P6
P70 - P77
I/O port P7
I/O
P80 - P87
I/O port P8
I/O
This is an input pin for HOLD request signal. The microcomputer enters into hold state while this signal is "L". ___ This is an input pin for RDY signal. The microcomputer enters into ready state while this signal is "L". This pin outputs the clock 1. These pins become a 5-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In addition to having the same functions as port P4, __ __ also function as I/O pins for timers these pins A0 to A3 and input pins for key input interrupt input (KI0 - KI3). In addition to having the same functions as port ___these pins also function as I/O pins for timer P4, ___ A4, input pins for external interrupt input (INT0 - INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock SUB output pin. In addition to having the same functions as port P4, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. In addition to having the same functions as port P4, these pins also function as I/O pins for UART 0 and UART 1.
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37733S4BFP has the same functions as the M37733MHBXXXFP except for the following : (1) The memory map is different. (2) The processor mode is different. (3) The reset circuit is different. (4) Pulse output port mode of timer A is available. (5) The function of ROM area modification is not available.
MEMORY
The memory map is shown in Figure 1. The address space has a capacity of 16 Mbytes and is allocated to addresses from 016 to FFFFFF16. The address space is divided by 64-Kbyte unit called bank. The banks are numbered from 016 to FF16. Built-in RAM and control registers for internal peripheral devices are assigned to bank 016. Addresses FFD616 to FFFF16 are the RESET and interrupt vector addresses and contain the interrupt vectors. Use ROM for memory of this address.
The 2048-byte area allocated to addresses from 8016 to 87F16 is the built-in RAM. In addition to storing data, the RAM is used as stack during a subroutine call or interrupts. Peripheral devices such as I/O ports, A-D converter, serial I/O, timer, and interrupt control registers are allocated to addresses from 016 to 7F16. A 256-byte direct page area can be allocated anywhere in bank 016 by using the direct page register (DPR). In the direct page addressing mode, the memory in the direct page area can be accessed with two words. Hence program steps can be reduced.
00000016 Bank 016 00FFFF16 01000016
00000016 00007F16 00008016
00000016 Internal peripheral devices control registers
refer to Fig. 2 for detail information
Internal RAM 2048 bytes
00007F16
Bank 116 00FFD616 01FFFF16
*******************
Interrupt vector table
A-D/UART2 trans./rece. UART1 transmission UART1 receive UART0 transmission UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2
00087F16
FE000016 Bank FE16 FEFFFF16 FF000016 Bank FF16 FFFFFF16 00FFD616 00FFFF16 00FFFE16
Timer A1 Timer A0
INT2/Key input INT1 INT0
Watchdog timer
DBC
BRK instruction Zero divide
RESET
: Internal : External
Fig. 1 Memory map
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation) 000000 000001 000002 Port P0 register 000003 Port P1 register 000004 Port P0 direction register 000005 Port P1 direction register 000006 Port P2 register 000007 Port P3 register 000008 Port P2 direction register 000009 Port P3 direction register 00000A Port P4 register 00000B Port P5 register 00000C Port P4 direction register 00000D Port P5 direction register 00000E Port P6 register 00000F Port P7 register 000010 Port P6 direction register 000011 Port P7 direction register 000012 Port P8 register 000013 000014 Port P8 direction register 000015 000016 000017 000018 000019 00001A 00001B 00001C Pulse output data register 1 00001D Pulse output data register 0 00001E A-D control register 0 00001F A-D control register 1 000020 A-D register 0 000021 000022 A-D register 1 000023 000024 A-D register 2 000025 000026 A-D register 3 000027 000028 A-D register 4 000029 00002A A-D register 5 00002B 00002C A-D register 6 00002D 00002E A-D register 7 00002F 000030 UART 0 transmit/receive mode register 000031 UART 0 baud rate register (BRG0) 000032 UART 0 transmission buffer register 000033 000034 UART 0 transmit/receive control register 0 000035 UART 0 transmit/receive control register 1 000036 UART 0 receive buffer register 000037 000038 UART 1 transmit/receive mode register 000039 UART 1 baud rate register (BRG1) 00003A UART 1 transmission buffer register 00003B 00003C UART 1 transmit/receive control register 0 00003D UART 1 transmit/receive control register 1 00003E UART 1 receive buffer register 00003F
Address (Hexadecimal notation) 000040 000041 000042 000043 000044 000045 000046 000047 000048 000049 00004A 00004B 00004C 00004D 00004E 00004F 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F
Count start flag One-shot start flag Up-down flag
Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency selection flag Waveform output mode register Reserved area (Note) UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1 A-D/UART2 trans./rece. interrupt control register UART 0 transmission interrupt control register UART 0 receive interrupt control register UART 1 transmission interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register
INT2/Key input interrupt control register
Note . Do not write to this address.
Fig. 2 Location of internal peripheral devices and interrupt control registers
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Pulse output port mode
The pulse motor drive waveform can be output by using plural internal timer A. Figure 3 shows a block diagram for pulse output port mode. In the pulse output port mode, two pairs of four-bit pulse output ports are used. Whether using pulse output port or not can be selected by waveform output selection bit (bit 0, bit 1) of waveform output mode register (6216 address) shown in Figure 4. When bit 0 of waveform output selection bit is set to "1", RTP10, RTP11, RTP12, and RTP13 are used as pulse output ports, and when bit 1 of waveform output selection bit is set to "1", RTP00, RTP01, RTP02, and RTP03 are used as pulse output ports. When bits 1 and 0 of waveform output selection bit are set to "1", RTP10, RTP11, RTP12, and RTP13, and RTP00, RTP01, RTP02, and RTP03 are used as pulse output ports. The ports not used as pulse output ports can be used as normal parallel ports, timer input/output or key input interruput input. In the pulse output port mode, set timers A0 and A2 to timer mode as timers A0 and A2 are used. Figure 5 shows the bit configuration of timer A0, A2 mode registers in pulse output port mode. Data can be set in each bit of the pulse output data register corresponding to four ports selected as pulse output ports. Figure 6
shows the bit configuration of the pulse output data register. The contents of the pulse output data register 1 (low-order four bits of 1C16 address) corresponding to RTP10, RTP11, RTP12, and RTP13 is output to the ports each time the counter of timer A2 becomes 000016. The contents of the pulse output data register 0 (low-order four bits of 1D16 address) corresponding to RTP00, RTP01, RTP02, and RTP03 is output to the ports each time the counter of timer A0 becomes 000016. Figure 7 shows example of waveforms in pulse output port mode. When "0" is written to a specified bit of the pulse output data register, "L" level is output to the corresponding pulse output port when the counter of corresponding timer becomes 000016, and when "1" is written, "H" level is output to the pulse output port. Pulse width modulation can be applied to each pulse output port. Since pulse width modulation involves the use of timers A1 and A3, activate these timers in pulse width modulation mode.
4 Pulse width modulation selection bit (Bit 4, 5 of 6216 address)
5
Pulse width modulation output by timer A3 Pulse width modulation output by timer A1
Timer A2 Pulse output data register 1 (1C16 address) D3 D2 D1 DTQ D D D Q Q Q RTP13 (P57) RTP12 (P56) RTP11 (P55) RTP10 (P54)
Data bus (even)
Data bus (odd)
D0
D11 D10 D9 D8 Pulse output data register 0 (1D16 address) Timer A0
D D D D T
Q Q Q Q
RTP03 (P53) RTP02 (P52) RTP01 (P51) RTP00 (P50)
Polarity selection bit (Bit 3 of 6216 address)
Fig. 3 Block diagram for pulse output port mode
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
RTP10, RTP11, RTP12, and RTP13 are applied pulse width modulation by timer A3 by setting the pulse width modulation selection bit by timer A3 (bit 5) of the waveform output mode register to "1". RTP00, RTP01, RTP02, and RTP03 are applied pulse width modulation by timer A1 by setting the pulse width modulation selection bit by timer A1 (bit 4) of the waveform output mode register to "1". The contents of the pulse output data register 0 can be reversed and output to pulse output ports RTP00, RTP01, RTP02, and RTP03 by the polarity selection bit (bit 3) of the waveform output mode register. When the polarity selection bit is "0", the contents of the pulse output data register 0 is output unchangeably, and when "1", the contents of the pulse output data register 0 is reversed and output. When pulse width modulation is applied, likewise the polarity reverse to pulse width modulation can be selected by the polarity selection bit.
76543210 00X1 00
Address Timer A0 mode register 5616 Timer A2 mode register 5816 Always "100" in pulse output port mode Not used in pulse output port mode Always "00" in pulse output port mode Clock source selection bit 0 0 : Select f2 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512
76543210 0
Fig. 5 Timer A0, A2 mode register bit configuration in pulse output port mode
Address Weveform output mode register 6216 Weveform output selection bit 0 0 : Parallel port 0 1 : RTP1 selected 1 0 : RTP0 selected 1 1 : RTP1 and RTP0 selected Polarity selection bit 0 : Positive polarity 1 : Negative polarity Pulse width modulation selection bit by timer A1 0 : Not modulated 1 : Modulated Pulse width modulation selection bit by timer A3 0 : Not modulated 1 : Modulated Always "0"
76543210
Address Pulse output data register 0 1D16 RTP00 output data RTP01 output data RTP02 output data RTP03 output data
76543210
Address Pulse output data register 1 1C16 RTP10 output data
Fig. 4 Waveform output mode register bit configuration
RTP11 output data RTP12 output data RTP13 output data
Fig. 6 Pulse output data register bit configuration
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Example of pulse output port (RTP10 - RTP13) Output signal at each time when timer A2 becomes 000016 RTP13 (P57)
RTP12 (P56)
RTP11 (P55)
RTP10 (P54)
Example of pulse output port (RTP10 - RTP13) when pulse width modulation is applied by timer A3. Output signal at each time when timer A2 becomes 000016 RTP13 (P57)
RTP12 (P56)
RTP11 (P55)
RTP10 (P54)
Example of pulse output port (RTP00 - RTP03) when pulse width modulation is applied by timer A1 with polarity selection bit = "1". Output signal at each time when timer A0 becomes 000016 RTP03 (P53)
RTP02 (P52)
RTP01 (P51)
RTP00 (P50)
Fig. 7 Example of waveforms in pulse output port mode
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
The bits 0 of processor mode register 0 as shown in Figure 8 is used to select which mode of microprocessor mode, and evaluation chip mode. Figure 9 shows functions of P00/A0 to P47 pins in each mode. The external memory area also changes when the mode changes. Figure 10 shows the memory map for each mode. The accessing of the external memory is affected by the BYTE pin, the bit 2 (wait bit) of processor mode register 0, and bit 0 (wait selection bit) of processor mode register 1.
* BYTE pin
When accessing the external memory, the level of the BYTE pin is used to determine whether to use the data bus as 8-bit width or 16bit width. The data bus width is 8 bits when the level of the BYTE pin is "H", and P20/A16/D0 to P27/A23/D7 pins become the data I/O pins. The data bus width is 16 bits when the level of the BYTE pin is "L", and both P20/A16/D0 to P27/A23/D7 pins and P10/A8/D8 to P17/A15/ D15 pins become the data I/O pins. When accessing the internal memory, the data bus width is always 16 bits regardless of the BYTE pin level.
76543210 0 1
Address Processor mode register 0 5E16 Processor mode bit 0 : Microprocessor mode 1 : Evaluation chip mode This bit must be "1" (becomes "1" after reset release) Wait bit 0 : Wait 1 : No Wait Software reset bit Reset occurs when this bit is set to "1"
76543210 Processor mode register 1 Wait selection bit 0 : Wait 0 1 : Wait 1
Address 5F16
Interrupt priority detection time selection bit 0 0 : Internal clock ! 7 0 1 : Internal clock ! 4 1 0 : Internal clock ! 2 This bit must be "0" Not used
Fig. 8 Processor mode register bit configuration
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
PM1 PM0 Mode Pin
E
1 0 Microprocessor mode
(Note)
1 1 Evaluation Chip mode
P00/A0 - P07/A7
P00/A0 P07/A7
Address A0-A7
Same as left
BYTE = "L" P10/A8/D8
E A8 to A15 P10/A8/D8 P17/A15/D15 E
- -
Address
Data(odd)
Same as left
E
A8 to A15
Address Data(odd)
P17/A15/D15
P20/A16/D0
E
P27/A23/D7
P30/R/W, P31/BHE, P32/ALE, P33/HLDA
HOLD, RDY, HOLD RDY P42/ P43 P47
1
P42/ 1, P43 to P47
Fig. 9 Relationship between pins P00 /A0 to P47 and processor modes Note. The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the 1 output _ in the microprocessor mode. In the microprocessor mode, signal E can also be fixed to "H" when the internal memory area is accessed.
-
BYTE = "H"
P10/A8/D8 P17/A15/D15
Address A8-A15
P10/A8/D8 P17/A15/D15
BYTE = "L"
E A16 to A23 P20/A16/D0 P27/A23/D7
- -
-
Ports P4, P5 and their direction registers are treated as 16-bit wide bus.
Address
Data(even)
Same as left
-
A16 to A23
Address
Data(even, odd)
E P20/A16/D0
A16 to A23
Address
Data(even, odd)
BYTE = "H"
P20/A16/D0 P27/A23/D7
P30/R/W P31/BHE P32/ALE P33/HLDA
-
E E
P27/A23/D7 Ports P4, P5 and their direction registers are treated as 16-bit wide bus.
-
R/W BHE ALE
Same as left
HLDA
E
HOLD RDY
HOLD RDY P42/ (Note) P43 P44 P45 P46 P47
VDA VPA DBC
1
MX QCL
I/O Port
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
As shown in Figure 11, when the external memory area is accessed with the processor mode register 0 (address 5E16) bit 2 (wait bit) cleared to "0", the access time can be extended compared with no wait (the wait bit is "1"). The access time is extended in two ways and this is selected with bit 0 (wait selection bit) of processor mode register 1 (address 5F16). When this bit is "1", the access time is 1.5 times compared to that for no wait. When this bit is "0", the access time is twice compared to that for no wait. At reset, the wait bit and the wait selection bit are "0". The accessing of internal memory area is performed in no wait mode regardless of the wait bit. The processor modes are described below.
Internal clock
Ai/Dj
Address
Data Address Data
Wait bit "1" (No wait)
E
ALE Access time Ai/Dj
Address
Data
Address
Data
Wait bit "0" (Wait 1)
E
ALE Access time Ai/Dj
Address Data Address
Microprocessor mode 0016 SFR 8016 RAM 87F16
Evaluation chip mode 216 A16 C16 SFR 8016 RAM 87F16
Wait bit "0" (Wait 0)
E
ALE Access time
Fig. 11 Relationship between wait bit, wait selection bit, and access time
(1) Microprocessor mode [10]
Microprocessor mode is entered by connecting the CNVss pin to Vcc and starting from reset. _ _ Signal E is output from pin E and is "L" during the data/instruction code read or data write term. When the internal memory area is read _ or written, E can be fixed to "H" by setting the signal output disable selection bit (bit 6 of oscillation circuit control register 0) to "1". P00/A0 to P07/A7 pins become address output pins. P10/A8/D8 to P17/A15/D15 pins have two functions depending on the level of the BYTE pin. When the BYTE pin level is "L", P10/A8/D8 to P17/A15/D15 pins function _ as an address output pin while E is "H" and as an odd address data _ I/O pin while E is "L". However, if an internal memory is read, external _ data is ignored while E is "L". When the BYTE pin level is "H", P10/A8/D8 to P17/A15/D15 pins function as an address output pin. When the BYTE pin level is "L", P20/A16/D0 to P27/A23/D7 pins function _ as an address output pin while E is "H" and as an even address data _ I/O pin while E is "L". However, if an internal memory is read, external _ data is ignored while E is "L". _ R/W is a read /write signal which indicates a read when it is "H" and a write when it is "L". ___ BHE is a byte high enable signal which indicates that an odd address is accessed when it is "L". Therefore, two bytes at even and odd addresses are accessed ___ simultaneously if address A0 is "L" and BHE is "L". ALE is an address latch enable signal used to latch the address signal from a multiplexed signal of address and data. The latch is transparent while ALE is "H" to let the address signal pass through and held while ALE is "L".
FFFFFF16
FFFFFF16
The shaded area is the external memory area.
Fig. 10 External memory area for each processor mode
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
HLDA is a hold acknowledge signal and is used to notify externally
____
when the microcomputer receives HOLD input and enters hold state. ____ HOLD is a hold request signal. It is an input signal used to put the ____ microcomputer in hold state. HOLD input is accepted when the internal clock falls from "H" level to "L" level while the bus is not used. P00/A0 to P07/A7 pins, P10/A8/D8 to P17/A15/D15 pins, P20/A16/D0 to _ ___ P27/A23/D7 pins, P30/R/W pin, and P31/BHE pin are floating while the microcomputer stays in hold state. These pins are floating after one ____ cycle of the internal clock later than HLDA signal changes to "L" level. At the removing of hold state, these ports are removed from ____ floating state after one cycle of internal clock later than HLDA signal changes to "H" level. ___ RDY is a ready signal. If this signal goes "L", the internal clock ___ stops at "L". RDY is used when slow external memory is attached. P42/ 1 pin is an output pin for clock 1 . The 1 output is ___ independent of RDY and does not stop even when internal clock ___ stops because of "L" input to the RDY pin. As shown in Table 2, 1 output can also be stopped with the signal output disable selection bit "1". In this case, write "1" to the port P42 direction register.
(2) Evaluation chip mode [11]
Evaluation chip mode is entered by applying voltage twice the VCC voltage to the CNVSS pin. This mode is normally used for evaluation tools. _ _ ___ ____ The functions of E, P00/A0 to P07/A7 pins, R/W, BHE, ALE, and HLDA are the same as those in microprocessor mode. P10/A8/D8 to P17/A15/D15 pins function as address output pins while _ _ E is "H" and as data I/O pin of odd addresses while E is "L" regardless of the BYTE pin level. However, if an internal memory is read, external _ data is ignored while E is "L". P20/A16/D0 to P27/A23/D7 pins function _ as address output pins while E is "H" and as data I/O pin of even _ addresses while E is "L" when the BYTE pin level is "L". However, if _ an internal memory is read, external data is ignored while E is "L". When the BYTE pin level is "H" or 2*VCC, port P2 functions as an _ address output pin while E is "H" and as data I/O pin of even and odd _ addresses while E is "L". However, if an internal memory is read, _ external data is ignored while E is "L". Port P4 and its data direction which are located at address 0A16 and 0C16 are treated differently in evaluation chip mode. When these
addresses are accessed, the data bus width is treated as 16 bits regardless of the BYTE pin level, and the access cycle is treated as internal memory regardless of the wait bit. ____ ___ The functions of HOLD and RDY are the same as those in microprocessor mode. Clock 1 from P42/ 1 pin is always output regardless of signal output disable selection bit. Ports P43 to P46 become MX, QCL, VDA, and VPA output pins ___ respectively. Port P47 becomes the DBC input pin. The MX signal normally contents of flag m, but the contents of flag x is output if the CPU is using flag x. QCL is the queue buffer clear signal. It becomes "H" when the instruction queue buffer is cleared, for example, when a jump instruction is executed. VDA is the valid data address signal. It becomes "H" while the CPU is reading data from data buffer or writing data to data buffer. It also becomes "H" when the first byte of the instruction (operation code) is read from the instruction queue buffer. VPA is the valid program address signal. It becomes "H" while the CPU is reading an instruction code from the instruction queue buffer. ___ DBC is the debug control signal and is used for debugging. Table 1 shows the relationship between the CNVSS pin input levels and processor modes.
Table 1. Relationship between CNVss pin input levels and processor modes CNVss Mode Description * Microprocessor Microprocessor mode upon Vss (* Evaluation chip) starting after reset. * Evaluation chip Evaluation chip mode only. 2 * Vcc
Table 2. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0) Processor mode
_
Pin
_
Function CM6 = "0"
_
CM6 = "1"
E
E is output when the internal/external memory
E is output only when the external memory
area is accessed. After WIT/STP instruction is executed, "H" is output. Microprocessor mode
1
Clock
1
is output.
area is accessed. "L" is output after WIT/STP instruction is executed. Standby state selection bit (bit 0 of port function control register) must be set to "1". "H"or "L" is output. (Output the content of P42 latch.) Port P42 direction register must be set to "1".
Note. Functions shown in Table 2 cannot be emulated in a debugger.
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
_____
The microcomputer is released from the reset state when the RESET pin is returned to "H" level after holding it at "L" level with the power source voltage at 5 V 10 %. Program execution starts at the address formed by setting address A23 - A16 to 0016, A15 - A8 to the contents of address FFFF16, and A7 - A0 to the contents of address FFFE16. Figure 12 shows the status of the internal registers during reset. Figure 13 shows an example of a reset circuit. If the stabilized clock
is input from the external to the main-clock oscillation circuit, the reset input voltage must be 0.9 V or less when the power source voltage reaches 4.5 V. If a resonator/oscillator is connected to the main-clock oscillation circuit, change the reset input voltage from "L" to "H" after the main-clock oscillation is fully stabilized.
Address Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register A-D control register 0 A-D control register 1 UART 0 transmit/receive mode register UART 1 transmit/receive mode register UART 0 transmit/receive control register 0 UART 1 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 1 transmit/receive control register 1 Count start flag One- shot start flag Up-down flag Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register
Address
(0416)*** (0516)*** (0816)*** (0916)*** (0C16)*** (0D16)*** (1016)*** (1116)*** (1416)***
0016 0016 0016 0000 0016 0016 0016 0016 0016
Watchdog timer frequency selection flag Waveform output mode register UART2 transmit/receive mode register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1
A-D/UART2 trans./rece. interrupt control register
(6116)*** (6216)*** 0 (6416)*** (6816)*** 000
0 00
0000000 1000
(6916)*** 0 0 0 0 0 0 1 0 (6C16)*** (6D16)*** (6E16)*** (6F16)*** 0 (7016)*** 00000 0016 00 00000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 1
(1E16)*** 0 0 0 0 0 ? ? ? (1F16)*** (3016)*** (3816)*** 000 0016 0016 11
UART 0 transmission interrupt control register (7116)*** UART 0 receive interrupt control register
(7216)***
UART 1 transmission interrupt control register (7316)*** UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register
INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register
(3416)*** 0 0 0 0 1 0 0 0 (3C16)*** 0 0 0 0 1 0 0 0 (3516)*** 0 0 0 0 0 0 1 0 (3D16)*** 0 0 0 0 0 0 1 0 (4016)*** (4216)*** (4416)*** (5616)*** (5716)*** (5816)*** (5916)*** (5A16)*** 0016 00000 0016 0016 0016 0016 0016 0016
(7416)*** (7516)*** (7616)*** (7716)*** (7816)*** (7916)*** (7A16)*** (7B16)*** (7C16)*** (7D16)*** (7E16)*** (7F16)***
(5B16)*** 0 0 1 0 0 0 0 0 (5C16)*** 0 0 1 (5D16)*** 0 0 1 (5E16)*** (5F16)*** (6016)*** FFF16 0000 0000 0016 0
Processor status register (PS) Program bank register (PG) Program counter (PCH) Program counter (PCL) Direct page register (DPR) Data bank register (DT)
000??0001?? 0016 Content of FFFF16 Content of FFFE16 000016 0016
Contents of other registers and RAM are undefined during reset. Initialize them by software.
Fig. 12 Microcomputer internal status during reset
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Power on
VCC
RESET
4.5V 0V
VCC
RESET
0V
0.9V
Note. In this case, stabilized clock is input from the external to the main-clock oscillation circuit. Perform careful evalvation at the system design level before using. Fig. 13 Example of a reset circuit
ADDRESSING MODES
The M37733S4BFP has 28 powerful addressing modes. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE - CHIP 16-BIT MICROCOMPUTERS for the details of each addressing mode.
MACHINE INSTRUCTION LIST
The M37733S4BFP has 103 machine instructions. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE - CHIP 16-BIT MICROCOMPUTERS for details.
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc AVcc VI Parameter Power source voltage Analog power____ voltage source Input voltage RESET, CNVss, BYTE Input voltage P10/A8/D8 - P17/A15/D15, P20/A16/D0 - P27/A23/D7, P43 - P47, P50 - P57, P60 - P67,___-___ P70 P77, P80 - P87, VREF, XIN, HOLD, RDY Output voltage P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, _ P20/A16/D0 - P27/A23/D7, P30/R/W, __ ___ P31/BHE, P32/ALE, P33/HLDA , P42/ 1, P43 - P47, P50 - P57, P60 - _ P67, P70 - P77, P80 - P87, XOUT, E Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to +7 -0.3 to +7 -0.3 to +12 -0.3 to Vcc + 0.3 Unit V V V V
VI
VO
-0.3 to Vcc + 0.3
V
Pd Topr Tstg
Ta = 25 C
300 -20 to +85 -40 to +150
mW C C
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V 10 %, Ta = -20 to +85 C, unless otherwise noted)
Symbol Vcc AVcc Vss AVss VIH VIH VIL VIL IOH(peak) Parameter f(XIN) : Operating Power source voltage f(XIN) : Stopped, f(XCIN) = 32.768 kHz Analog power source voltage Power source voltage Analog power source voltage ___ ___ High-level input voltage HOLD, RDY, P43____ P50 - P57, P60 - P67, P70 - P77, - P47, P80 - P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3) High-level input voltage ___ ___ - P17/A15/D15, P20/A16/D0 - P27/A23/D7 P10/A8/D8 Low-level input voltage HOLD, RDY, P43____ P50 - P57, P60 - P67, P70 - P77, - P47, P80 - P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3) Low-level input voltage P10/A8/D8 - P17/A15/D15, P20/A16/D0 - P27/A23/D7 High-level peak output current P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, _ ___ P20/A16/D0 - P27/A23/D7, P30/R/W, P31/BHE, ___ P32/ALE, P33/HLDA, P42/ 1, P43 - P47, P50 - P57, P60 - P67, P70 - P75, P80 - P87 High-level average output current P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, _ ___ P20/A16/D0 - P27/A23/D7, P30/R/W, P31/BHE, ____ P32/ALE, P33/HLDA, P42/ 1, P43 - P47, P50 - P57, P60 - P67, P70 - P75, P80 - P87 Low-level peak output current P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, _ ___ P20/A16/D0 - P27/A23/D7, P30/R/W, P31/BHE, ____ P32/ALE, P33/HLDA, P42/ 1, P43, P54 - P57, P60 - P67, P70 - P75, P80 - P87 Low-level peak output current P44 - P47, P50 - P53 Low-level average output current P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, _ ___ P20/A16/D0 - P27/A23/D7, P30/R/W, P31/BHE, ____ P32/ALE, P33/HLDA, P42/ 1, P43, P54 - P57, P60 - P67, P70 - P75, P80 - P87 Low-level average output current P44 - P47, P50 - P53 Main-clock oscillation frequency (Note 4) Sub-clock oscillation frequency Min. 4.5 2.7 Limits Typ. 5.0 Vcc 0 0 0.8 Vcc 0.5 Vcc 0 0 Vcc Vcc 0.2Vcc 0.16Vcc -10 Max. 5.5 5.5 Unit V V V V V V V V mA
IOH(avg)
-5
mA
IOL(peak) IOL(peak) IOL(avg)
10 20 5
mA mA mA
IOL(avg) f(XIN) f(XCIN)
32.768
15 25 50
mA MHz kHz
Notes 1. Average output current is the average value of a 100 ms interval. _ ___ 2. ____ The sum of IOL(peak) for ports P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, P20/A16/D0 - P27/A23/D7, P30/R/W, P31/BHE, P32/ALE, P33/ HLDA and P8 must be 80 mA or less, the sum of IOH(peak) for ports P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, P20/A16/D0 - P27/A23/ _ ___ ____ D7, P30/R/W, P31/BHE, P32/ALE, P33/HLDA and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = "1". 4. The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = "1".
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to +85 C, f(XIN) = 25 MHz, unless otherwise noted)
Symbol Parameter Test conditions Min. 3 Limits Typ. Max. Unit High-level output voltage P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, ___ P20/A16/D0 - P27/A23/D7, P33/HLDA, P42/ 1, IOH = -10 mA P43 - P47, P50 - P57, P60 - P67, P70 - P77, P80 - P87 High-level output voltage P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, ___ IOH = -400 A P20/A16/D0 - P27/A23/D7, P33/HLDA, P42/ 1 _ ___ IOH = -10 mA High-level output voltage P30/R/W, P31/BHE, P32/ALE
IOH = -400 IOH = -400
1,
VOH
V
VOH VOH VOH
4.7 3.1 4.8 3.4 4.8 2 2 0.45 1.9 0.43 1.6 0.4 0.4 0.2 0.1 0.1 1 0.5 0.4 0.4 5
V V V
A A
_
High-level output voltage E Low-level output voltage P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, ___ P20/A16/D0 - P27/A23/D7, P33/HLDA, P42/ P43, P54 - P57, P60 - P67, P70 - P77, P80 - P87 Low-level output voltage P44 - P47, P50 - P53 Low-level output voltage P00/A0 - P07/A7, P10/A8/D8 - P17/A15/D15, ___ P20/A16/D0 - P27/A23/D7, P33/HLDA, P42/
_ ___
IOH = -10 mA
VOL VOL VOL VOL VOL VT+ - VT- VT+ - VT- VT+ - VT- VT+ - VT- IIH
IOL = 10 mA IOL = 20 mA
V V V V V V V V V V V A
1
IOL = 2 mA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA
Low-level output voltage P30/R/W, P31/BHE, P32/ALE
_
Low-level output voltage E
____ ___
IIL
Hysteresis ___ ___ ____ ____ ____ ____ TB2IN, HOLD, RDY, TA0IN - TA4IN, TB0IN - INT0 - INT2, ADTRG, __ CTS0, CTS1, CTS2, CLK0, __ CLK1, CLK2, KI0 - KI3 _____ Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current P10/A8/D8 - P17/A15/D15, P20/A16/D0 - P27/A23/D7, P43 - P47, P50 - P57, P60 - P67, P70 - P77, P80 - P87, ____ XIN, RESET, CNVss, BYTE Low-level input current P10/A8/D8 - P17/A15/D15, P20/A16/D0 - P27/A23/D7, P43 - P47, P50 - P53, P60,____ - P67, P70 - P77, P61, P65 P80 - P87, XIN, RESET, CNVss, BYTE
VCC = 5 V
VI = 5 V
VI = 0 V
VI = 0 V, without a pull-up transistor VI = 0 V, with a pull-up transistor When clock is stopped
-5
A
-5
A
IIL
Low-level input current P54 - P57, P62 - P64
-0.25 2
-0.5
-1.0
mA V
VRAM
RAM hold voltage
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to +85 C, unless otherwise noted)
Symbol Parameter Test conditions VCC = 5 V, f(XIN) = 25 MHz (square waveform), (f(f2) = 12.5 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 5 V, f(XIN) = 25 MHz (square waveform), (f(f2) = 1.5625 MHz), f(XCIN) = Stopped, in operating (Note 1) VCC = 5 V, When external bus f(XIN) = 25 MHz (square waveform), is in use, output f(XCIN) = 32.768 kHz, pins are open, and when a WIT instruction is executed (Note 2) other pins are VSS. VCC = 5 V, f(XIN) = Stopped, f(XCIN) = 32.768 kHz, in operating (Note 3) VCC = 5 V, f(XIN) = Stopped, f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 C, when clock is stopped Ta = 85 C, when clock is stopped Min. Limits Typ. Max. Unit
11.4
22.8
mA
1.6
3.2
mA
ICC
Power source current
10
20
A
60
120
A
5
10
A
1 20
A A
Notes 1. This applies when the main clock external input selection bit = "1", the main clock division selection bit = "0", and the signal output stop bit = "1". 2. This applies when the main clock external input selection bit = "1" and the system clock stop bit at wait state = "1". 3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4. This applies when the XCOUT drivability selection bit = "0" and the system clock stop bit at wait state = "1".
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = -20 to +85 C, f(XIN) = 25 MHz, unless otherwise noted (Note)) Symbol -- -- RLADDER tCONV VREF VIA Parameter Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage Test conditions VREF = VCC VREF = VCC VREF = VCC Min. Limits Typ. Max. 10 3 25 VCC VREF Unit Bits LSB k s V V
10 9.44 2 0
Note. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHz.
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to +85 C, f(XIN) = 25 MHz, unless otherwise noted (Note 1))
Notes 1. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHZ. 2. Input signal's rise/fall time must be 100 ns or less, unless otherwise noted.
External clock input
Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time (Note 1) External clock input high-level pulse width (Note 2) External clock input low-level pulse width (Note 2) External clock rise time External clock fall time Limits Min. 40 15 15 Max. Unit ns ns ns ns ns
8 8
Notes 1. When the main clock division selection bit = "1", the minimum value of tc = 80 ns. 2. When the main clock division selection bit = "1", values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.
Microprocessor mode
Symbol tsu(P4D-E) tsu(P5D-E) tsu(P6D-E) tsu(P7D-E) tsu(P8D-E) th(E-P4D) th(E-P5D) th(E-P6D) th(E-P7D) th(E-P8D) tsu(D-E) tsu(RDY- 1) tsu(HOLD- 1) th(E-D) th( 1-RDY) th( 1-HOLD) Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Data input setup time ___ RDY input setup time ____ HOLD input setup time Data input hold time ___ RDY input hold time ____ HOLD input hold time Parameter Limits Min. 60 60 60 60 60 0 0 0 0 0 32 55 55 0 0 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Timer A input
Symbol tc(TA) tw(TAH) tw(TAL)
(Count input in event counter mode) parameter Limits Min. 80 40 40 Max. Unit ns ns ns
TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width
Timer A input (Gating input in timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note) TAiIN input high-level pulse width (Note) TAiIN input low-level pulse width (Note) parameter Limits Min. 320 160 160 Max. Unit ns ns ns
Note. Limits change depending on f(XIN). Refer to "DATA FORMULAS."
Timer A input (External trigger input in one-shot pulse mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note) TAiIN input high-level pulse width TAiIN input low-level pulse width parameter Limits Min. 320 80 80 Max. Unit ns ns ns
Note. Limits change depending on f(XIN). Refer to "DATA FORMULAS."
Timer A input (External trigger input in pulse width modulation mode)
Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width parameter Limits Min. 80 80 Max. Unit ns ns
Timer A input (Up-down input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Timer A input (Two-phase pulse input in event counter mode)
Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjIN input cycle time TAjIN input setup time TAjOUT input setup time parameter Limits Min. 800 200 200 Max. Unit ns ns ns
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MITSUBISHI MICROCOMPUTERS
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edges count) TBiIN input high-level pulse width (both edges count) TBiIN input low-level pulse width (both edges count) Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns
Timer B input (Pulse period measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Parameter Limits Min. 320 160 160 Max. Unit ns ns ns
Note. Limits change depending on f(XIN). Refer to "DATA FORMULAS."
Timer B input (Pulse width measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Parameter Limits Min. 320 160 160 Max. Unit ns ns ns
Note. Limits change depending on f(XIN). Refer to "DATA FORMULAS."
A-D trigger input
Symbol
____
Parameter
ADTRG input cycle time (minimum allowable trigger) ____ ADTRG input low-level pulse width
Limits Min. 1000 125 Max.
Unit ns ns
tc(AD) tw(ADL)
Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time
____ ___
Parameter
Limits Min. 200 100 100 0 30 90 Max.
Unit ns ns ns ns ns ns ns
80
External interrupt INTi input, key input interrupt KIi input
Symbol
___
Parameter
INTi input high-level pulse width INTi input low-level pulse width __ KIi input low-level pulse width
___
Limits Min. 250 250 250 Max.
Unit ns ns ns
tw(INH) tw(INL) tw(KIL)
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DATA FORMULAS Timer A input (Gating input in timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 8 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) Max. Unit ns ns ns
Timer A input (External trigger input in one-shot pulse mode)
Symbol tc(TA) TAiIN input cycle time Parameter Limits Min. 8 ! 109 2 * f(f2) Max. Unit ns
Timer B input (In pulse period measurement mode or pulse width measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Parameter Limits Min. 8 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) Max. Unit ns ns ns
Note. f(f2) expresses the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 9 in data sheet "M37733MHBXXXFP".
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16-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS
(VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to +85C, f(XIN) = 25 MHz, unless otherwise noted (Note))
Microprocessor mode
Symbol td(E-P4Q) td(E-P5Q) td(E-P6Q) td(E-P7Q) td(E-P8Q) Parameter Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time Test conditions Limits Min. Max. 80 80 80 80 80 Unit ns ns ns ns ns
Fig. 14
Note. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHz.
A0-A7 A 8/D 8 - A 23/D 7 R/W
BHE
50 pF
ALE
HLDA
P4 P5 P6 P7 P8
1 E
Fig. 14 Measuring circuit for each pin
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16-BIT CMOS MICROCOMPUTER
Microprocessor mode
(VCC = 5 V 10 %, VSS = 0 V, Ta = 25 C, f(XIN) = 25 MHz, unless otherwise noted (Note 1)) Symbol td(An-E) Address output delay time Parameter Test (Note2) Wait mode conditions No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Limits Min. 12 87 12 75 18 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 22 57 5 45 9 Fig. 14 15 4 10 45 No wait Wait 1 Wait 0 18 50 130 5 20 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 12 87 12 87 18 18 0 18 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
td(A-E) th(E-An) tw(ALE)
Address output delay time Address hold time ALE pulse width
tsu(A-ALE)
Address output setup time
th(ALE-A)
Address hold time
td(ALE-E) td(E-DQ) th(E-DQ) tw(EL) tpxz(E-DZ) tpzx(E-DZ) td(BHE-E)
ALE output delay time Data output delay time Data hold time
_
E pulse width
Floating start delay time Floating release delay time
___
BHE output delay time
td(R/W-E) th(E-BHE) th(E-R/W) td(E- td(
1)
_
R/W output delay time
___
BHE hold time
_
R/W hold time
1
output delay time
____
1-HLDA)
HLDA output delay time
Notes 1. This applies when the main clock division selection bit = "0" and f(f2) = 12.5 MHz. 2. No wait : Wait bit = "1". Wait 1 : The external memory area is accessed with wait bit = "0" and wait selection bit = "1". Wait 0 : The external memory area is accessed with wait bit = "0" and wait selection bit = "0".
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16-BIT CMOS MICROCOMPUTER
Bus timing data formulas
(VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to +85 C, f(XIN) = 25 MHz (Max.), unless otherwise noted (Note 1)) Symbol Parameter Wait mode No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 th(E-An) Address hold time No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 td(E-DQ) th(E-DQ) Data output delay time Data hold time
_
td(An-E)
Address output delay time
td(A-E)
Address output delay time
tw(ALE)
ALE pulse width
tsu(A-ALE)
Address output setup time
Limits Min. 1 ! 109 - 28 2 * f(f2) 9 3 ! 10 - 33 2 * f(f2) 9 1 ! 10 - 28 2 * f(f2) 9 3 ! 10 - 45 2 * f(f2) 1 ! 109 - 22 2 * f(f2) 1 ! 109 - 18 2 * f(f2) 9 2 ! 10 - 23 2 * f(f2) 9 1 ! 10 - 35 2 * f(f2) 9 2 ! 10 - 35 2 * f(f2) 9 1 ! 109 2 * f(f2) 4 1 ! 10 2 * f(f2)
9
Max.
Unit ns ns ns ns ns ns ns ns ns ns
th(ALE-A)
Address hold time
- 25
ns ns
td(ALE-E)
ALE output delay time
- 30 45
ns ns ns ns ns 5 ns ns ns ns ns ns ns ns 18 ns
No wait Wait 1 Wait 0
tw(EL) tpxz(E-DZ) tpzx(E-DZ)
E pulse width
1 ! 109 2 * f(f2) 2 ! 109 2 * f(f2) 4 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 3 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 3 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 1 ! 109 2 * f(f2) 0
- 22 - 30 - 30
Floating start delay time Floating release delay time
___
- 22 - 28 - 33 - 28 - 33 - 22 - 22
td(BHE-E)
BHE output delay time
No wait Wait 1 Wait 0
td(R/W-E)
_
R/W output delay time
No wait Wait 1 Wait 0
___
th(E-BHE) th(E-R/W) td(E-
1)
BHE hold time
_
R/W hold time
1
output delay time
Notes 1. This applies when the main-clock division selection bit = "0". 2. f(f2) expresses the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 9 in data sheet "M37733MHBXXXFP".
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16-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tr tf tc tw(H) tw(L)
XIN
E
td(E-P4Q)
Port P4 output
tsu(P4D-E)
Port P4 input
th(E-P4D)
td(E-P5Q)
Port P5 output
tsu(P5D-E)
Port P5 input
th(E-P5D)
td(E-P6Q)
Port P6 output
tsu(P6D-E)
Port P6 input
th(E-P6D)
td(E-P7Q)
Port P7 output
tsu(P7D-E)
Port P7 input
th(E-P7D)
td(E-P8Q)
Port P8 output
tsu(P8D-E)
Port P8 input
th(E-P8D)
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
tc(TA) tw(TAH) TAiIN input
tw(TAL)
tc(UP) tw(UPH) TAiOUT input tw(UPL)
In event count mode
TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising)
th(TIN-UP)
tsu(UP-TIN)
In event counter mode (When two-phase pulse input is selected) TAjIN input
tsu(TAjIN-TAjOUT)
tc(TA)
tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN)
TAjOUT input
tsu(TAjOUT-TAjIN)
tc(TB) tw(TBH) TBiIN input tw(TBL)
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16-BIT CMOS MICROCOMPUTER
tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH) CLKi
tw(CKL)
th(C-Q) TxDi td(C-Q) RxDi tsu(D-C) th(C-D)
tw(INL)
INTi input Kli input
tw(INH) tw(KNL)
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16-BIT CMOS MICROCOMPUTER
Microprocessor mode (When wait bit = "1")
1
E
RDY input
tsu(RDY-
1)
th(
1-RDY)
(When wait bit = "0")
1
E
RDY input
tsu(RDY-
1)
th(
1-RDY)
(When wait bit = "1" or "0" in common)
1
tsu(HOLD-
HOLD input
1)
th(
1-HOLD)
td(
HLDA output
1-HLDA)
td(
1-HLDA)
Test conditions * VCC = 5 V 10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
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16-BIT CMOS MICROCOMPUTER
Microprocessor mode (No wait : When wait bit = "1")
tw(L)
tw(H)
tf
tr
tc
XIN
1
td(E-
1)
td(E- tw(EL)
1)
E
td(An-E)
th(E-An)
An
Address
Address
Address
tw(ALE)
td(ALE-E)
ALE
th(ALE-A) tsu(A-ALE) th(E-DQ) tpxz(E-DZ) tpzx(E-DZ)
Am/Dm
Address
td(A-E)
Data
td(E-DQ)
Address
Address
th(E-D) tsu(D-E)
DmIN
Data
td(BHE-E) BHE
th(E-BHE)
td(R/W-E)
th(E-R/W)
R/W
Test conditions * Vcc = 5 V 10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
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16-BIT CMOS MICROCOMPUTER
Microprocessor mode (Wait 1 : The external memory area is accessed when wait bit = "0" and wait selection bit = "1".)
tw(L) XIN
tw(H)
tf tr
tc
1
td(E-
1)
td(E- tw(EL)
1)
E
td(An-E) An Address
th(E-An) Address Address
tw(ALE) ALE
td(ALE-E)
th(ALE-A) tsu(A-ALE) Am/Dm Address Data th(E-DQ) tpxz(E-DZ) tpzx(E-DZ) Address
Address
td(A-E)
td(E-DQ) tsu(D-E)
th(E-D)
DmIN td(BHE-E)
BHE
Data th(E-BHE)
td(R/W-E) R/W
th(E-R/W)
Test conditions * Vcc = 5 V 10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
Microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = "0" and wait selection bit = "0".)
tw(L) XIN
tw(H)
tf tr
tc
1
td(E-
1)
td(E- tw(EL)
1)
E
td(An-E) An Address
th(E-An) Address Address
tw(ALE) ALE
td(ALE-E)
tsu(A-ALE)
th(ALE-A) th(E-DQ) tpxz(E-DZ) Address tpzx(E-DZ) Address
Am/Dm
Address td(A-E)
Data td(E-DQ)
tsu(D-E) DmIN th(E-BHE) td(BHE-E)
BHE
th(E-D)
Data
td(R/W-E) R/W
th(E-R/W)
Test conditions * Vcc = 5 V 10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
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16-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
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16-BIT CMOS MICROCOMPUTER
MEMO
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M37733S4BFP
16-BIT CMOS MICROCOMPUTER
MEMO
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16-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
(c) 1996 MITSUBISHI ELECTRIC CORP. H-LF432-A KI-9607 Printed in Japan (ROD) New publication, effective Jul. 1996. 36 Specifications subject to change without notice.

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